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publication number s25fl016m revision a amendment 0 issue date july 13, 2004 advance information s25fl family (serial peripheral interface) s25fl016m 16 megabit cmos 3.0 volt flash memory with 50 mhz spi bus interface distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6 v read and program operations ? memory architecture ? thirty-two sectors with 512 kb each ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? program cycles are on a page by page basis ? erase ? 1.5 s typical sector erase time ? 48 s typical bulk erase time ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? jedec standard two-byte electronic signature ? res instruction one-byte electronic signature for backward compatibility ? process technology ? manufactured on 0.20 m mirrorbit tm process technology ? package option ? industry standard pinouts ? 16-pin so package (300 mils) ? 8-contact wson package (8x6mm), no-lead performance characteristics ? speed ? 50 mhz clock rate (maximum) ? power saving standby mode ? standby mode 50 a (max) ? deep power down mode 1 a (typical) memory protection features ? memory protection ? w# pin works in conjunction with status register bits to protect specified memory areas ? status register block protection bits (bp2, bp1, bp0) in status register configure parts of memory as read- only software features ? spi bus compatible serial interface
2 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information general description the s25fl016m device is a 3.0 volt (2.7 v to 3.6 v) single power supply flash memory device. s25fl016m consists of thirty-two sectors, each with 512 kb memory. data appears on si input pin when inputting data into the memory and on the so output pin when outputting data from the memory. the devices are designed to be programmed in-system with the standard system 3.0 volt v cc supply. the memory can be programmed 1 to 256 bytes at a time, using the page program in - struction. the memory supports sector erase and bulk erase instructions. each device requires only a 3.0 volt power supply (2.7 v to 3.6 v) for both read and write functions. internally generated and regulated voltages are provided for the program op - erations. this device does not require v pp supply.
july 13, 2004 s25fl016m_a0_e s25fl family (serial peripheral interface) s25fl016m 3 preliminary table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . .2 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . .3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . .5 input/output descriptions . . . . . . . . . . . . . . . . . . . .5 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ordering information . . . . . . . . . . . . . . . . . . . . . . . .7 table 1. s25fl valid combinations table . . . . . . . . . . . . . . . .7 signal description .....................................................................................8 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 1. bus master and memory devices on the spi bus . . . . 9 figure 2. spi modes supported. . . . . . . . . . . . . . . . . . . . . . . 9 operating features . . . . . . . . . . . . . . . . . . . . . . . . 10 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. protected area sizes (s25fl016m). . . . . . . . . . . . . . 11 hold condition modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. hold condition activation . . . . . . . . . . . . . . . . . . . 12 memory organization . . . . . . . . . . . . . . . . . . . . . . 13 table 3. sector address table ? s25fl016m . . . . . . . . . . . . . 13 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 4. write enable (wren) instruction sequence............. 15 write disable (wrdi)...........................................................................16 figure 5. write disable (wrdi) instruction sequence ............ 16 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 6. read status register (rdsr) instruction sequence . 17 figure 7. status register format . . . . . . . . . . . . . . . . . . . . 17 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. write status register (wrsr) instruction sequence 19 table 5. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . .19 read data bytes (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. read data bytes (read) instruction sequence . . . . 20 read data bytes at higher speed (fast_read) . . . . . . . . . . 20 figure 10. read data bytes at higher speed (fast_read) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 11. read identification (rdid) instruction sequence and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 12. page program (pp) instruction sequence . . . . . . . 23 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 13. sector erase (se) instruction sequence . . . . . . . . 24 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 14. bulk erase (be) instruction sequence. . . . . . . . . . 25 deep power down (dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 15. deep power down (dp) instruction sequence . . . . 26 release from deep power down (res) . . . . . . . . . . . . . . . . . .26 figure 16. release from deep power down instruction sequence 27 release from deep power down and read electronic signature (res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 17. release from deep power down and read electronic signature (res) instruction sequence. . . . . . . . . . 28 power-up and power-down . . . . . . . . . . . . . . . . . . 28 figure 18. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19. power-down and voltage drop. . . . . . . . . . . . . . . 29 table 6. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . 30 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . 30 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . 30 absolute maximum ratings . . . . . . . . . . . . . . . . . 30 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 30 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . .31 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. ac measurements i/o waveform......................... 32 table 8. test specifications . . . . . . . . . . . . . . . . . . . . . . . . 32 table 9. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21. spi mode 0 (0,0) input timing. . . . . . . . . . . . . . . 34 figure 22. spi mode 0 (0,0) output timing. . . . . . . . . . . . . . 34 figure 23. hold# timing . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 24. write protect setup and hold timing during wrsr when srwd=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 36 s016 wide?16-pin plastic small outline 300mils body width package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 wson 8-contact (8x6mm) no-lead package . . . . . . . . . . . . 37 revision summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information block diagram cs# sck si so gnd v cc hold# sram ps logic array - l array - r rd data path io x d e c
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 5 advance information connection diagrams input/output descriptions sck = serial clock input si = serial data input so = serial data output cs# = chip select input w# = write protect input hold# = hold input v cc = supply voltage input gnd = ground input 1 2 3 4 16 15 14 13 hold# vcc nc nc nc nc si sck 5 6 7 8 12 11 10 9 w# gnd nc nc nc nc cs# so 16-pin plastic small outline package (so)
6 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information logic symbol cs# so w# gnd si sck hold# v cc
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 7 advance information ordering information the ordering part number is formed by a valid combination of the following: ta b l e 1 . s25fl valid combinations table notes: 1. type 1 is standard. specify other options as required. 2. contact your local sales office for availability. 3. package marking omits leading ?s25? and speed, package, and leading digit of model number form ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. s25fl 016 m 0l m a 1 00 1 packing type 1 = tube (standard; see note 1 ) 3 = 13? tape and reel ( note 2 ) model number (additional ordering options) 00 = no additional ordering options temperature range i = industrial (-40 c to + 85c) package materials a = standard f = lead (pb)-free ( note 2 ) package type m = 16- pin plastic small outline package n = 8-contact wson package speed 0l = 50mhz device technology m = 0.20 m mirrorbit? process technology density 016 = 16mb device family s25fl spansion tm memory 3.0 volt-only, serial peripheral interface (spi) flash memory s25fl valid combinations package marking (see note 3) base ordering part number speed option package & temperature model number packing type s25fl016m 0l mai, mfi, nai, nfi ( note 2 ) 00 1, 3 ( note 1 ) fl016m + (temp) + (last digit of model number)
8 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information signal description signal data output (so): this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (sck). serial data input (si): this input signal is used to transfer data serially into the device. it receives instructions, add resses, and the data to be programmed. values are latched on the rising edge of serial clock (sck). serial clock (sck): this input signal provides the timing of the serial interface. instructions, addresses, and data present at the serial data input (si) are latched on the rising edge of serial clock (sck). data on serial data output (so) changes after the falling edge of serial clock (sck). chip select (cs#): when this input signal is high , the device is deselected and serial data output (so) is at high impedance. unless an internal program, erase or write status register cycle is in progress, the device will be in standby mode. driving chip select (cs#) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select (cs#) is required prior to the start of any instruction. hold (hold#): the hold (hold#) signal is used to pause any serial communi - cations with the device without deselecting the device. during the hold instruction, the serial da ta output (so) is high impedance, and serial data input (si) and s erial clock (sck) are don?t care. to start the hold condition, the device must be selected, with chip select (cs#) driven low. write protect (w#): the main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the bp1 and bp0 bits of the status register). spi modes these devices can be driven by a microcon troller with its spi peripheral running in either of the two following modes: ? cpol = 0, cpha = 0 ? cpol = 1, cpha = 1 for these two modes, input data is latched in on the rising edge of serial clock (sck), and output data is available from the falling edge of serial clock (sck). the difference between the two modes, as shown in figure 2 , is the clock polarity when the bus master is in standby and not transferring data: ? sck remains at 0 for (cpol = 0, cpha = 0) ? sck remains at 1 for (cpol = 1, cpha = 1)
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 9 advance information figure 1. bus master and memory devices on the spi bus note: the write protect (w#) and hold (hold#) signals should be driven, high or low as appropriate. figure 2. spi modes supported spi interface with (cpol, cpha) = (0, 0) or (1, 1) bus master cs3 cs2 cs1 spi memory device spi memory device spi memory device cs# w# hold# cs# w# hold# cs# w# hold# sck so si sck so si sck so si so si sck msb msb sck sck si so cpha cpol 00 11 cs#
10 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information operating features all data into and out of the device is shifted in 8-bit chunks. page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle. to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be pro - grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on th e same page of memory. sector erase, or bulk erase the page program (pp) instruction allows bits to be programmed from 1 to 0. be - fore this can be applied, the bytes of the memory need to be first erased to all 1?s (ffh) before any programming. this can be achieved in two ways: 1) a sector at a time using the sector erase (se) instruction, or 2) throughout the entire memory, using the bulk erase (be) instruction. polling during a write, program, or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst-case delay. the write in progress (wip) bit is provided in the status register so that the applica - tion program can monitor its value, polling it to establish when the previous write cycle, program cycle, or erase cycle is complete. active power and standby power modes when chip select (cs#) is low, the device is enabled, and in the active power mode. when chip select (cs#) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes into the standby power mode. the device consumption drops to i sb . this can be used as an extra deep power down on mechanism, when the device is not in active use, to protect the device from inadvertent write, program, or erase instructions. status register the status register contains a number of status and control bits, as shown in fig - ure 7 , that can be read or set (as appr opriate) by specific instructions ? wip bit: the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. ? wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. ? bp2, bp1, bp0 bits: the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. ? srwd bit: the status register write disable (srwd) bit is operated in con- junction with the write protect (w#) signal. the status register write disable (srwd) bit and write protect (w#) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits.
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 11 advance information protection modes the spi memory device boasts the following data protection mechanisms: ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ?power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion ? the block protect (bp2, bp1, bp0) bits allow part of the memory to be con- figured as read-only. this is the software protected mode (spm). ? the write protect (w#) signal works in cooperation with the status register write disable (srwd) bit to enable write-protection. this is the hardware protected mode (hpm). ? program, erase and write status register instructions are checked to verify that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. ta b l e 2 . protected area sizes (s25fl016m). hold condition modes the hold (hold#) signal is used to pa use any serial communications with the device without resetting the clocking se quence. hold (hold#) signal gates the clock input to the device. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with chip select (cs#) low. the hold condition starts on the falling edge of the hold (hold#) signal, provided that this coincides with serial clock (sck) being low (as shown in figure 3 ). the hold condition ends on the rising edge of the hold (hold#) signal, provided that this coincides with serial clock (sck) being low. protected memory area (top level) status register content memory content bp2 bit bp1 bit bp0 protected area unprotected area 0 0 0 0 none 000000h-1fffffh 1/32 0 0 1 1f0000h-1fffffh 000000h-1effffh 1/16 0 1 0 1e0000h-1fffffh 000000h-1dffffh 1/8 0 1 1 1c0000h-1fffffh 000000h-1bffffh 1/4 1 0 0 180000h-1fffffh 000000h-17ffffh 1/2 1 0 1 100000h-1fffffh 000000h-0fffffh all 1 1 0 000000h-1fffffh none all 1 1 1 000000h-1fffffh none
12 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information if the falling edge does not coincide with serial clock (sck) being low, the hold condition starts after serial clock (sck) next goes low. similarly, if the rising edge does not coincide with serial clock (sck) being low, the hold condition ends after serial clock (sck) next goes low ( figure 3 ). during the hold condition, the serial data output (so) is high impedance, and serial data input (si) and serial clock (sck) are don?t care. normally, the device remains selected, with chip select (cs#) driven low, for the entire duration of the hold condition. this ensures that the state of the internal logic remains unchanged from the moment of entering the hold condition. if chip select (cs#) goes high while the device is in the hold condition, this has the effect of resetting the internal logi c of the device. to restart communication with the device, it is necessary to driv e hold (hold#) high, and then to drive chip select (cs#) low. this prevents the device from going back to the hold condition. figure 3. hold condition activation sck hold# hold condition (standard use) hold condition (non-standard use)
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 13 advance information memory organization the memory is organized as: ? s25fl016m: thirty-two sectors of 512 kbit each ? each page can be individually programmed (bits are programmed from 1 to 0). ? the device is sector or bulk erasable (bits are erased from 0 to 1). ta b l e 3 . sector address table ? s25fl016m sector address range sa31 1f0000h 1fffffh sa30 1e0000h 1effffh sa29 1d0000h 1dffffh sa28 1c0000h 1cffffh sa27 1b0000h 1bffffh sa26 1a0000h 1affffh sa25 190000h 19ffffh sa24 180000h 18ffffh sa23 170000h 17ffffh sa22 160000h 16ffffh sa21 150000h 15ffffh sa20 140000h 14ffffh sa19 130000h 13ffffh sa18 120000h 12ffffh sa17 110000h 11ffffh sa16 100000h 10ffffh sa15 0f0000h 0fffffh sa14 0e0000h 0effffh sa13 0d0000h 0dffffh sa12 0c0000h 0cffffh sa11 0b0000h 0bffffh sa10 0a0000h 0affffh sa9 090000h 09ffffh sa8 080000h 08ffffh sa7 070000h 07ffffh sa6 060000h 06ffffh sa5 050000h 05ffffh sa4 040000h 04ffffh sa3 030000h 03ffffh sa2 020000h 02ffffh sa1 010000h 01ffffh sa0 000000h 00ffffh
14 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information instructions all instructions, addresses, and data are shifted in and out of the device, starting with the most significant bit. serial data input (si) is sampled on the first rising edge of serial clock (sck) after chip se lect (cs#) is driven low. then, the one- byte instruction code must be shifted in to the device, most significant bit first, on serial data input (si), each bit bein g latched on the rising edges of serial clock (sck). the instruction set is listed in ta b l e 4 . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. chip select (cs#) must be driven high after the last bit of the in - struction sequence has been shifted in. in the case of a read data bytes (read), read status register (rdsr), read data bytes at higher speed (fast_read) and read identification (rdid) instruc - tions, the shifted-in instruction sequence is followed by a data-out sequence. chip select (cs#) can be driven high after any bit of the data-out sequence is being shifted out to terminate the transaction. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren), or write disable (wrdi) instruc - tion, chip select (cs#) must be driv en high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (cs#) must driven high when the number of clock pulses after chip select (cs#) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 15 advance information ta b l e 4 . instruction set write enable (wren) the write enable (wren) instruction ( figure 4 ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), erase (se or be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (cs#) low, sending the instruction code, and then driving chip select (cs#) high. figure 4. write enable (wren) instruction sequence instruction description one-byte instruction code address bytes dummy byte data bytes status register operations wren write enable 06h (0000 0110) 0 0 0 wrdi write disable 04h (0000 0100) 0 0 0 rdsr read from status register 05h (0000 0101) 0 0 1 to infinity wrsr write to status register 01h (0000 0001) 0 0 1 read operations read read data bytes 03h (0000 0011) 3 0 1 to infinity fast_read read data bytes at higher speed 0bh (0000 1011) 3 1 1 to infinity rdid read identification 9fh (1001 1111) 0 0 1 to 3 erase operations se sector erase d8h (1101 1000) 3 0 0 be bulk (chip) erase c7h (1100 0111) 0 0 0 program operations pp page program 02h (0000 0010) 3 0 1 to 256 deep power down savings mode operations dp deep power down b9h (1011 1001) 0 0 0 res release from deep power down abh (1010 1011) 0 0 0 release from deep power down and read electronic signature abh (1010 1011) 0 3 1 to infinity cs# sck si so high impedance instruction 01 23 4 5 67
16 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information write disable (wrdi) the write disable (wrdi) instruction ( figure 5 ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (cs#) low, sending the instruction code, and then driving chip select (cs#) high. the write enable latch (wel) bit is reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion figure 5. write disable (wrdi) instruction sequence 0 1 2 34 5 6 7 sck si so high impedance instruction cs#
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 17 advance information read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase, or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status reg - ister continuously, as shown in figure 6 . figure 6. read status register (rdsr) instruction sequence figure 7. status register format the status and control bits of th e status register are as follows: srwd bit: the status register write disable (s rwd) bit is operated in conjunc - tion with the write protect (w#) sign al. the status register write disable (srwd) bit and write protect (w#) signal allow the device to be put in the hard - ware protected mode (when the status re gister write disable (srwd) bit is set to 1, and write protect (w#) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instructio n is no longer accepted for execution. bp2, bp1, bp0 bits: the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are writte n with the write status register (wrsr) instruction. when one or both of the block protect (bp2, bp1, bp0) bits is set to 1, the relevant memory area (as defined in ta b l e 2 ) becomes protected against page program (pp), and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not instruction high impedance msb msb status register out status register out 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 7 6 5 4 3 2 10 7 6 5 4 3 2 1 0 7 so si sck cs# status register write disable block protect bits write enable latch bit write in progress bit srwd 0 0 bp1 bp0 wel wip b7 b0 bp2
18 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information been set. the bulk erase (be) instruction is executed if, and only if, all block pro - tect (bp2, bp1, bp0) bits are 0. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set; when set to 0, the internal write enable latch is reset and no write status register, pro - gram or erase instruction is accepted. wip bit: the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. this bit is a read only bit and is read by executing a rdsr instruction. if this bit is 1, such a cycle is in progress, if it is 0, no such cycle is in progress. write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be acce pted, a write enable (wren) instruction must previously have been executed. af ter the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (w rsr) instruction is entered by driving chip select (cs#) low, followed by the instruction code and the data byte on serial data input (si). the instruction sequence is shown in figure 8 . the write status register (wrsr) instructio n has no effect on bits b6, b5, b1 and b0 of the status register. bits b6 and b5 are always read as 0. chip select (cs#) must be driven high af ter the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not exe - cuted. as soon as chip select (cs#) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. at some un - specified time before the cycle is completed, the write enable latch (wel) is reset. the wrsr instruction enables the user to select one of seven levels of protection. the s25fl016m is divided into eight arra y segments. the top thirty-second, six - teenth, eighth, quarter, half or all of the memory segments can be protected (as defined in table 1). the data within a selected segment is therefore read-only. the write status register (wrs r) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w#) signal. the status register write disable (srwd) bit and write protect (w#) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruct ion cannot be executed once the hard - ware protected mode (hpm) is entered.
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 19 advance information figure 8. write status register (wrsr) instruction sequence ta b l e 5 . protection modes note: as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 2 . the protection features of the device are summarized in ta b l e 5 . when the status register write disable (srw d) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction, regardless of the whether write protect (w#) is driven high or low. when the status register write disable (s rwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w#): ? if write protect (w#) is driven high, it is possible to write to the status reg- ister provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect (w#) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp1, bp0) bits of the status register, are also hardware pro- tected against data modification. regardless of the order of the two even ts, the hardware protected mode (hpm) can be entered: w# signal srwd bit mode write protection of the status register protected area (note 1) unprotected area (note 1) 1 1 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program and erase (se, be) ready to accept page program and sector erase instructions 1 0 0 0 0 1 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program and erase (se, be) ready to accept page program and sector erase instructions high impedance msb instruction status register in cs# sck si so 0 12 3 4 5 6 7 8 9 10 11 12 13 14 15
20 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information ? by setting the status register write disable (srwd) bit after driving write protect (w#) low ? or by driving write protect (w#) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protecte d mode (hpm) once entered is to pull write protect (w#) high. if write protect (w#) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp2, bp1, bp0) bits of the status register, can be used. read data bytes (read) the read instruction reads the memory at the specified sck frequency (f sck ) with a maximum speed of 33 mhz. the device is first selected by driving chip select (cs#) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23- a0), each bit being latched-in during the rising edge of serial clock (sck). then the memory contents, at that address, are shifted out on serial data output (so), each bit being shifted out, at a frequency f sck , during the falling edge of serial clock (sck). the instruction sequence is shown in figure 9 . the first byte addressed can be at any location. the address automatically increments to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 00000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes (read) instruction, while a program, erase, or write cycle is in progress, is rejected without having any effect on the cycle that is in progress. figure 9. read data bytes (read) instruction sequence read data bytes at higher speed (fast_read) the fast_read instruction reads the memory at the specified sck frequency (f sck ) with a maximum speed of 50 mhz. the device is first selected by driving chip select (cs#) low. the instruction code for (fast_read) instruction is fol - instruction 24-bit address high impedance msb msb data out 1 data out 2 0 31 32 33 34 35 36 37 38 39 30 23 28 10 9 8 7 6 5 4 3 2 1 7 6 5 23 22 21 4 3 2 1 0 3 2 1 0 7 so si sck cs#
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 21 advance information lowed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched- in during the rising edge of serial clock (sck). then the memory contents, at that address, are shifted out on serial data output (so), each bit being shifted out, at a maximum frequency f sck , during the falling edge of serial clock (sck). the instruction sequence is shown in figure 10 . the first byte addressed can be at any location. the address automatically increments to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single (fast_read) instruction. when the highest address is reached, the address counter rolls over to 00000h, allowi ng the read sequence to be continued indefinitely. the (fast_read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effect s on the cycle that is in progress. figure 10. read data bytes at higher speed (fast_read) instruction sequence read identification (rdid) the read identification (rdid) instruction allows the 8-bit manufacturer identifi - cation to be read, followed by two bytes of the device identification. the manufacturer identification byte is assigned by jedec, and has a value of 01h for spansion? products. the device identifi cation is assigned by the device man - ufacturer, and indicates the memory type in the first byte (02h), and the memory capacity of the device in the second byte (15h). any read identification (rdid) instruction executed while an erase, program, or write status register cycle is in progress is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (cs#) low. then, the 8-bit in - struction code for the instruction is shifted in, with each bit being latched in on si during the rising edge of sck. this is followed by the 24-bit device identifica - tion, stored in the memory, being shifted out on serial data output (so), with each bit being shifted out during the falling edge of serial clock (sck). the instruction sequence is shown in figure 11 . cs# sck si so instruction 24-bit address dummy byte high impedance data out 1 data out 2 msb msb 01 2 34 56 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 23 22 21 3 2 1 0 7 654 3 2 1 0 7 6 5 4 3 210 7
22 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information figure 11. read identification (rdid) instruction sequence and data-out sequence driving cs# high after the device identifi cation has been read at least once ter - minates the read_id instruction. the read identification (rdid) instruction can also be terminated by driving cs# hi gh at any time during data output. when chip select (cs#) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. table 1. read identification (rdid) data-out sequence page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is ent ered by driving chip select (cs#) low, followed by the instruction code, three add ress bytes and at least one data byte on serial data input (si). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 12 . if more than 256 bytes are sent to the device, the addressing will wrap to the beginning of the same page, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if fewer than 256 data bytes are se nt to device, they are correctly pro - grammed at the requested addresses with out having any effects on the other bytes of the same page. chip select (cs#) must be driven high af ter the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, manufacturer identification device identification memory type memory capacity 01h 02h 15h 0 1 2 456 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 instruction msb manufacturer identification device identification high impedance 0 1 2 3 13 14 15 cs# sck si so 3
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 23 advance information the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is com - pleted, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page that is protected by the block protect (bp2, bp1, bp0) bits (see ta b l e 2 ) is not executed. figure 12. page program (pp) instruction sequence sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been de - coded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (cs#) low, followed by the instruction code, and three address bytes on serial data input (si). any address inside the sector (see ta b l e 2 ) is a valid address for the sector erase (se) instruction. chip select (cs#) must be driven low for the entire du - ration of the sequence. the instruction sequence is shown in figure 13 . chip select (cs#) must be driven high aft er the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed sector erase cycle (whose duration is tse) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is com - pleted, the write enable latch (wel) bit is reset. 0 34 33 32 31 30 29 28 10 9 8 7 6 5 4 3 2 1 35 36 37 38 39 46 45 44 43 42 41 40 47 48 49 50 51 52 53 54 55 2073 2072 2076 2075 2074 2079 2078 2077 23 22 21 3 21 07 6 5 43 2 1 0 data byte 1 24-bit address instruction data byte 2 data byte 3 data byte 256 msb msb msb msb msb sck si sck si 7 65 4 3 2 1 0 76 54 321 0 7 6 5 43210 cs# cs#
24 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information a sector erase (se) instruction applied to any memory area that is protected by the block protect (bp2, bp1, bp0) bits (see ta b l e 2 ) is not executed. figure 13. sector erase (se) instruction sequence bulk erase (be) the bulk erase (be) instruction sets to 1 (ffh) all bits inside the entire memory. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been de - coded, the device sets the write enable latch (wel). the bulk erase (be) instruction is entered by driving chip select (cs#) low, fol - lowed by the instruction code, on serial data input (si). no address is required for the bulk erase (be) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 14 . chip select (cs#) must be driven high aft er the eighth bit of the last address byte has been latched in, otherwise the bulk erase (be) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is com - pleted, the write enable latch (wel) bit is reset. a bulk erase (be) instruction is executed only if all the block protect (bp2, bp1, bp0) bits (see ta b l e 2 ) are set to 0. the bulk erase (be) instruction is ignored if one or more sectors are protected. cs# sck si msb instruction 24 bit address 01 2 3 4 5 6 7 8 9 10 28 29 30 31 23 22 21 3 2 1 0
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 25 advance information figure 14. bulk erase (be) instruction sequence deep power down (dp) the deep power down (dp) instruction puts the device in the lowest current mode of 1 a typical. it is recommended that the standard stan dby mode be used for the lowest power current draw, as well as the deep power down (dp) as an extra software protec - tion mechanism when this device is not in active use. in this mode, the device ignores all write, program and erase instructions. chip select (cs#) must be driven low for the entire duration of the sequence. the deep power down (dp) instruction is entered by driving chip select (cs#) low, followed by the instruction code on serial data input (si). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 15 . driving chip select (cs#) high after the eighth bit of the instruction code has been latched puts the device in deep power down mode. the deep power down mode can only be entered by executing the deep power down (dp) instruction to reduce the standby current (from i sb to i dp as specified in ta b l e 7 ). as soon as chip select (cs#) is driven high, it requires a delay of t dp currently in progress before deep power down mode is entered. once the device has entered the deep power down mode, all instructions are ig - nored except the release from deep power down (res) and read electronic signature. this releases the device from the deep power down mode. the re - lease from deep power down and read electronic signature (res) instruction also allows the electronic signature of the device to be output on serial data out - put (so). the deep power down mode automatically stops at power-down, and the device always powers up in the standby mode. any deep power down (dp) instruction, while an erase, program or wrsr cycle is in progress, is rejected without havi ng any effect on the cycle in progress. 01 2 4 56 7 instruction cs# sck si 3
26 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information figure 15. deep power down (dp) instruction sequence release from deep power down (res) the release from deep power down (res) instruction provides the only way to exit the deep power down mode. once the device has entered the deep power down mode, all instructions are ignored except the release from deep power down (res) instruction. executing this instruction takes the device out of deep power down mode. the release from deep power down (res) instruction is entered by driving chip select (cs#) low, followed by the instruction code on serial data input (si). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16 . driving chip select (cs#) high after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time, still insures that the device is put into standby mode. if the device was previously in the deep power down mode, though, the transition to the stand-by power mode is delayed by t res , and chip select (cs#) must remain high for at least t res(max) , as specified in ta b l e 9 . once in the stand- by power mode, the device waits to be se lected, so that it can receive, decode and execute instructions. cs# sck si standby mode deep power down mode instruction 0 1 234 56 7 t dp
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 27 advance information figure 16. release from deep power down instruction sequence release from deep power down and read electronic signature (res) once the device has entered deep power down mode, all instructions are ignored except the res instruction. the res instruction can also be used to read the old- style 8-bit electronic signature of the device on the so pin. the res instruction always provides access to the electronic signature of the device (except while an erase, program or wrsr cycle is in progress), and can be applied even if dp mode has not been entered. any res instruction executed while an erase, program or wrsr cycle is in progress is not decoded, and has no effect on the cycle in progress. the device features an 8-bit electronic signature, whose value for the s25fl016m is 14h. this can be read using res instruction. the device is first selected by driving chip select (cs#) low. the instruction code is followed by 3 dummy bytes, each bit bein g latched-in on serial data input (si) during the rising edge of s erial clock (sck). then, the 8-bit electronic signature, stored in the memory, is shifted out on serial data output (so), each bit being shifted out during the falling edge of serial clock (sck). the instruction sequence is shown in figure 17 . the release from deep power down and read electronic signature (res) is ter - minated by driving chip select (cs#) high after the electronic signature has been read at least once. sending additional clock cycles on serial clock (sck), while chip select (cs#) is driven low, causes the electronic signature to be out - put repeatedly. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power down mode, the tran - sition to the stand-by power mode is immediate. if the device was previously in the deep power down mode, though, the transition to the standby mode is de - layed by t res , and chip select (cs#) must remain high for at lease t res(max) , as specified in ta b l e 9 . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. cs# sck si 0 1 23 4 5 6 7 instruction deep power down mode t res standby mode
28 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information figure 17. release from deep power down and read electronic signature (res) instruction sequence power-up and power-down the device must not be selected at pow er-up or power-down (that is, cs# must follow the voltage applied on v cc ) until v cc reaches the correct value as follows: ? v cc (min) at power-up, and then for a further delay of t pu (as described in ta b l e 6 ) ? v ss at power-down for a minimum delay of t pd before power-up a simple pull-up resistor on chip select (cs#) can usually be used to insure safe and proper power-up and power-down. the device ignores all instructions until a time delay of t pu (as described in ta b l e 6 ) has elapsed after the moment that v cc rises above the minimum v cc thresh - old. however, correct operation of the device is not guaranteed if by this time v cc is still below v cc (min). no write status register, program or erase instructions should be sent until t pu after v cc reaches the minimum v cc threshold. at power-up, the device is in standby mode (not deep power down mode) and the wel bit is reset. during power-down or voltage drops, the power down must drop below the v cc (low) for a minimum period of t pd for the device to initialize correctly on power up. (see figure 19 ). normal precautions must be taken for supply rail decoupling to stabilize the v cc feed. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins (this ca pacitor is generally of the order of 0.1 f). at power-down, when v cc drops from the operating voltage to below the mini - mum v cc threshold, all operations are disabled and the device does not respond to any instructions. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, data corruption can result.) cs# sck si so 3 dummy bytes high impedance msb deep power down mode standby mode 0 1 2 3 4567 8 9 10 28 29 30 31 32 33 34 35 36 37 38 electronic id out instruction t res 23 22 21 3 2 10 7 654 32 1 0 msb
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 29 advance information figure 18. power-up timing figure 19. power-down and voltage drop v cc v cc (max) v cc (min) full device access t pu time vcc (max) vcc (min) vcc (low) no device access allowed device access allowed t pu t pd time
30 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information ta b l e 6 . power-up timing initial delivery state the device is delivered with all bits set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). maximum rating stressing the device above the rating listed in the absolute maximum ratings section below may cause p ermanent damage to the device. these are stress rat - ings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings ambient storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c voltage with respect to ground: all inputs and i/os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 v to 4.5 v operating ranges ambient operating temperature (t a ) commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c positive power supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 v to 3.6 v note: operating ranges define those limits between which functionality of the device is guaranteed . symbol parameter min max unit v cc(min) v cc (minimum) 2.7 v v cc(low) v cc (low) v t pu v cc (min) to device operation 4 ms t pd v cc (low) duration ns
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 31 advance information dc characteristics this section summarizes the dc and ac characteristics of the device. designers should check that the operating conditions in their circuit match the measure - ment conditions specified in the test specifications in ta b l e 8 , when relying on the quoted parameters. cmos compatible ta b l e 7 . dc characteristics notes: typical values are at t a = 25 c and 3.0 v. parameter description test conditions (see (see note notes:) ) min typ. max unit v cc supply voltage 2.7 3 3.6 v i cc1 active read current sck = 0.1 v cc /0.9v cc 33 mhz 6 ma sck = 0.1 v cc /0.9v cc v cc = 3.0v 50 mhz 11 ma i cc2 active page program current cs# = v cc 20 ma i cc3 active wrsr current cs# = v cc 24 ma i cc4 active sector erase current cs# = v cc 24 ma i cc5 active bulk erase current cs# = v cc 24 ma i sb standby current v cc = 3.0 v cs# = v cc 50 a i dp deep power down current v cc = 3.0 v cs# = v cc 1 10 a i li input leakage current v in = gnd to v cc 1 a i lo output leakage current v in = gnd to v cc 1 a v il input low voltage ?0.3 0.3 v cc v v ih input high voltage 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min 0.4 v v oh output high voltage i oh = ?0.1 ma v cc ? 0.2 v
32 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information test conditions figure 20. ac measurements i/o waveform ta b l e 8 . test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc input levels input and output timing reference level s 0.5 v cc
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 33 advance information ac characteristics ta b l e 9 . ac characteristics note: 1. typical program and erase times assume the following conditions: 25 c, vcc = 3.0v; 10, 000 cycles; checkerboard data pattern 2. under worst-case conditions of 90 c; vcc = 2.7v; 100,000 cycles 3. not 100% tested symbol parameter min typ max unit f sck sck clock frequency read instruction d.c. 33 mhz f sck sck clock frequency for: fast_read, pp, se, be, dp, res, wren, wrdi, rdsr, wrsr d.c. 50 mhz t crt clock rise time (slew rate) 0.1 v/ns t cft clock fall time (slew rate) 0.1 v/ns t wh sck high time 9 ns t wl sck low time 9 ns t cs cs# high time 100 ns t css (see note 3) cs# setup time 5 ns t csh (see note 3) cs# hold time 5 ns t hd (see note 3) hold# setup time (relative to sck) 5 ns t cd (see note 3) hold# hold time (relative to sck) 5 ns t hc hold# setup time (relative to sck) 5 ns t ch hold# hold time (relative to sck) 5 ns t v output valid 10 ns t ho output hold time 0 ns t hd:dat data in hold time 5 ns t su:dat data in setup time 5 ns t r input rise time 5 ns t f input fall time 5 ns t lz (see note 3) hold# to output low z 10 ns t hz (see note 3) hold# to output high z 10 ns t dis (see note 3) output disable time 10 ns t wps (see note 3) write protect setup time 15 ns t wph (see note 3) write protect hold time 15 ns t w write status register time 65 ms t dp cs# high to deep power down mode 3 s t res release dp mode 30 s t pp page programming time 1.5 (see note 1) 3 (see note 2) ms t se sector erase time 1.5 (see note 1) 3 (see note 2) sec t be bulk erase time 48 (see note 1) 96 (see note 2) sec
34 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information ac characteristics figure 21. spi mode 0 (0,0) input timing figure 22. spi mode 0 (0,0) output timing cs# sck si so t csh t css t csh t css t crt t cft msb in lsb in high impedance t su:dat t hd:dat t cs cs# sck so lsb out t wh t wl t dis t v t ho t v t ho
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 35 advance information ac characteristics figure 23. hold# timing figure 24. write protect setup and hold timing during wrsr when srwd=1 t ch t hz t cd t hd t hc t lz cs# sck so si hold# w# cs# sck si so high impedance t wps t wph
36 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information physical dimensions s016 wide?16-pin plastic small outline 300mils body width package
july 13, 2004 s25fl016m_00_a0_e s25fl family (serial peripheral interface) s25fl016m 37 advance information wson 8-contact (8x6mm) no-lead package 3408\ 16-038.28 a notes: 1. dimensioning and tolerancing conforms to asme y14.5m-1994. 2. all dimensions are in millimeters, sym is in degrees. 3. n is the total number of terminals. 4. dimension b applies to metallized terminal and is measured between 0.15 and 0.30 mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. nd refers tot he number of terminals on d side. 6. maximum package warpage is 0.05 mm. 7. maximum allowable burrs is 0.076 mm in all directions . 8. pin #1 id on top will be laser marked. 9. bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. 10. a maximum 0.15 mm pull back (l1) may be present. quad flat no lead packages (wsnb) - plastic dimensions symbol min nom max note e 1.27 bsc n83 nd 4 5 l 0.45 0.50 0.55 b 0.35 0.40 0.45 4 d2 4.70 4.80 4.90 e2 6.30 6.40 6.50 d 6.00 bsc e 8.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 l1 0.15 max. 10 0 --- 12 2 k 0.20 min. side view a1 a 9. seating plane c 0.05 c 0.10 c top view b e a d n 8. 0 .30 dia typ. 2 1 2x c 0.10 2x c 0.10 bottom view nx l d2/2 2 1 d2 9. (datum a) pin #1 id r0.20 e2/2 e2 k 4. nx b n-1 e n 5. (nd-1) x e see detail "a " c m . 0.05 b a c m . 0.10 detail "a" datum a 4. 10. l1 terminal tip e e/2 l
38 s25fl family (serial peripheral interface) s25fl016m s25fl016m_00_a0_e july 13, 2004 advance information revision summary revision a0 (july 13, 2004) initial release. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear re action control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liab le to you and/or any third party for any claims or damages ari sing in connection with above-men - tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures in to your facility and equipment such as redu ndancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au - thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in t his document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 spansion llc. all rights reserved. spansion, the spansion logo, mirrorbit, comb inations thereof, and expressflash are trademarks of spansion llc. other company an d product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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